Altera_Forum
Honored Contributor
12 years agoBus Error
Hi,
I am currently working on an OpenCL application with multiple kernels targeted to Altera FPGA. Upon execution, the application breaks with an error message " bus error ". In order to trace the place of error I just added certain print statements. To my surprise after the addition of the print statements, the execution completed without printing any error message. Can anyone Explain this behavior? How should I handle this error in case I confront it again in future ? Also I find the message " cvp failed " coming up even for sample vector addition application. Is there a way to tackle this error ? Thanks