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Altera_Forum's avatar
Altera_Forum
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16 years ago

Bus contention because of the FPGA.

Hey guys, I have a BIDIR pin in my design file now that is not connected to any logic. Since that pin is connected to a DSP, I have been having bus contention problems. I know for sure that the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

A bus-line must be set to 'Z' (tri-stated) in idle state. You can do this also for unused bus lines. 

GPIO <= (others => 'Z');