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Altera_Forum's avatar
Altera_Forum
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16 years ago

Bus contention because of the FPGA.

Hey guys,

I have a BIDIR pin in my design file now that is not connected to any logic. Since that pin is connected to a DSP, I have been having bus contention problems. I know for sure that the FPGA is the culprit.

The only difference between a functional design (when the pin is connected to some logic) and a non-functional design (pin is not connected to any logic) is:,

Info: Pin GPIO[1] has VCC driving its datain port

Currently, on the oscillioscope, yes I can see that the FPGA is driving the pin high, how do I avoid that?

Thanks.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Compilers do not honour your assignments if it does not do anything.

    I wonder why you want bidir pin but without any logic. At least you can insert dummy logic to read/write the pin
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    A bus-line must be set to 'Z' (tri-stated) in idle state. You can do this also for unused bus lines. 

    GPIO <= (others => 'Z');
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    If the port is not synthesized due to a lack of logic, you can try setting the Unused Pin behavior to Input tri-stated with weak pull-up.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Thanks adding a when else code.. with tri-state during idle has solved it.