Building PCIe core in FPGA when using OpenCL

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hi folks ,

I am trying to make a hetrogenous computing system (cpu + gpu + fpga) that can be programmed using OpenCL as my research project . So for that I started studying about altera's work on FPGA and OpenCL. Basic idea is that fpga is connected to the cpu through PCIe and fpga is programmed with OpenCL using altera's sdk for OpenCL. But the problem is how do they build the required pcie core and other memory interconnects in the FPGA . As i know , that cannot be done using OpenCL. So how do they realy do it ?

Could anyone please help me with this ?

Thank you.

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Hi,

The PCI-E core is handled automatically by the SDK. It's an Altera IP on which the OpenCL kernel you develop will connect. You don't have to bother about it, neither do you about the memory controller. All in all, you just write your code as you would for a CPU or GPU. You will not do any single line of VHDL or verilog.

BTW, you might want to have a look at this (http://www.alteraforum.com/forum/showthread.php?t=47400).

Thnak alot smith !

But while reading more on this topic , i found out that they do this through board support package which includes PICe fascility and other interconnects. Are you talking about such a thing or that PCIe core is solely built by the altera SDK ?

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Thnak alot smith !

But while reading more on this topic , i found out that they do this through board support package which includes PICe fascility and other interconnects. Are you talking about such a thing or that PCIe core is solely built by the altera SDK ?

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Indeed, the SDK needs the BSP which is provided by the board vendor. The PCI-E core is a hard IP in the case of the stratix v (https://www.altera.com/en_us/pdfs/literature/ug/ug_s5_pcie.pdf).