Building a composed component with a instance that has a SYSTEM_INFO parameter

I think I almost understand what you're trying to do here. The component you're attempting to add is the SPI (4-Wire Serial) Altera FPGA IP (altera_avalon_spi). With the usual flow by adding the component manually into the system, the Platform Designer (PD) is able to generate the HDL successfully.

I added the SPI (4-Wire Serial) Altera FPGA IP component, resolved any errors as needed, and then went to File > Export System as .tcl Component. PD will generated a _hw.tcl file.

If you cross-check the _hw.tcl, you'll notice that there are parameter values set in the _hw.tcl, which I suspect are missing in your current my_composed_component —and that’s likely what causes the error message during your composed_component HDL generation.

Regards,

Richard Tan

# _hw.tcl file for test
package require -exact qsys 14.0

# module properties
set_module_property NAME {test_export}
set_module_property DISPLAY_NAME {test_export_display}

# default module properties
set_module_property VERSION {1.0}
set_module_property GROUP {default group}
set_module_property DESCRIPTION {default description}
set_module_property AUTHOR {author}

set_module_property COMPOSITION_CALLBACK compose
set_module_property opaque_address_map false

proc compose { } {
# Instances and instance parameters
# (disabled instances are intentionally culled)
add_instance clk_0 clock_source 24.1
set_instance_parameter_value clk_0 {clockFrequency} {50000000.0}
set_instance_parameter_value clk_0 {clockFrequencyKnown} {1}
set_instance_parameter_value clk_0 {resetSynchronousEdges} {NONE}

add_instance spi_0 altera_avalon_spi 24.1
set_instance_parameter_value spi_0 {clockPhase} {0}
set_instance_parameter_value spi_0 {clockPolarity} {0}
set_instance_parameter_value spi_0 {dataWidth} {8}
set_instance_parameter_value spi_0 {disableAvalonFlowControl} {0}
set_instance_parameter_value spi_0 {insertDelayBetweenSlaveSelectAndSClk} {0}
set_instance_parameter_value spi_0 {insertSync} {0}
set_instance_parameter_value spi_0 {lsbOrderedFirst} {0}
set_instance_parameter_value spi_0 {masterSPI} {1}
set_instance_parameter_value spi_0 {numberOfSlaves} {1}
set_instance_parameter_value spi_0 {syncRegDepth} {2}
set_instance_parameter_value spi_0 {targetClockRate} {128000.0}
set_instance_parameter_value spi_0 {targetSlaveSelectToSClkDelay} {0.0}

# connections and connection parameters
add_connection clk_0.clk spi_0.clk clock

add_connection clk_0.clk_reset spi_0.reset reset

# exported interfaces
add_interface clk clock sink
set_interface_property clk EXPORT_OF clk_0.clk_in
add_interface reset reset sink
set_interface_property reset EXPORT_OF clk_0.clk_in_reset
add_interface spi_0_external conduit end
set_interface_property spi_0_external EXPORT_OF spi_0.external
add_interface spi_0_irq interrupt sender
set_interface_property spi_0_irq EXPORT_OF spi_0.irq
add_interface spi_0_spi_control_port avalon slave
set_interface_property spi_0_spi_control_port EXPORT_OF spi_0.spi_control_port

# interconnect requirements
set_interconnect_requirement {$system} {qsys_mm.clockCrossingAdapter} {HANDSHAKE}
set_interconnect_requirement {$system} {qsys_mm.enableEccProtection} {FALSE}
set_interconnect_requirement {$system} {qsys_mm.insertDefaultSlave} {FALSE}
set_interconnect_requirement {$system} {qsys_mm.maxAdditionalLatency} {1}
}

Thanks Richard.

I did not knew that it is possible to create the _hw.tcl directly from platform designer. That is brilliant and simplify things a lot.
I have now successfully created a composed with one altera_avalon_spi and 2 altera_avalon_pio instances and called it myCircuit_hw.tcl
Additionally I have created a myCircuit_sw.tcl for the component.

The component is integrated in a parent qsys file with niosv processor and compiles.

When I generate the BSP the, BSP editor shows three Modules, but not the driver defined in the myCircuit_sw.tcl
All three modules have some dependecy. Therefore I want to not only link them in HW, but also have a single SW driver, that handles the communication with the SPI and both PIOs.

I saw that you created a new post for your follow-up question.

Since the initial question has been resolved, I will be transitioning this thread to community support.

If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

The community users will be able to help you on your follow-up questions.

Thank you and have a great day!

Best Regards,

Richard Tan