Bug Report: Verilog ?: handling and sign extension

I have a couple of Quartus II Verilog standard compliance related bug reports of which this is the first one. If this is not the right place to report bugs: please point me in the right direction..

Consider the following test case:

module issue_001(a, b, y);
  input  a;
  input  b;
  output  y;
  // the ?: must evaluate to the max width of both cases,
  // even if we can be sure that always the smaller case gets selected
  assign y = &( 1 ? a : b );
endmodule

The output of this module should be constant zero. Here is a short analysis of why this is so:

Sec. 5.1.13 of the Verilog Standard (IEEE Std 1364-2005), which describes the ?: statement, states:

[...] If the lengths of expression2 and expression3 are different, the shorter operand shall be

lengthened to match the longer and zero-filled from the left (the high-order end).

So with the condition beeing constant true, the expression in the parentheses must evaluate to {1'b0, a} and not simply a becasue of the size difference of a and b, thus the &-reduce operator should always see at least this one zero-bit and thus always return 0.

But Quartus does not perform the zero filling and therefore produces an incorrect result, which is equivalent to assign y = &a;.

In my tests I have synthesized the module with

quartus_map issue_001 --source=issue_001.v --family="Cyclone III"
quartus_fit issue_001
quartus_eda issue_001 --formal_verification --tool=conformal

Crosscheck: Vivado 2013.4, Isim 14.7 and Modelsim 10.1d implement this correctly. Interestingly XST 14.7 suffers from the same bug. (It is the only bug in my list so far that can be found in two tools.)

Note: This is a bug report. I don't need support.