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Altera_Forum's avatar
Altera_Forum
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12 years ago

Bug Report: Verilog ?: handling and sign extension

I have a couple of Quartus II Verilog standard compliance related bug reports of which this is the first one. If this is not the right place to report bugs: please point me in the right direction.. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

This is not the right place to report bugs, you need to file a support request.

I'm not so familiar with Verilog syntax rules, but from a "how synthesis works" viewpoint, I understand why Quartus is apparently skipping the resize operation for a constant condition.