Bug report: synthesis optimizes out the signal if data type is declared in generic package

Hi Ean,

I am feeding some data into the i port of the design and monitoring the o_bug port. As expected, the o_bug port is equal to the i port.

Here is the testbench:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bug_tb is
end bug_tb;
architecture test of bug_tb is
    signal i:      std_logic_vector(17 downto 0);
    signal o_bug:  std_logic_vector(16 downto 0); 
begin
    stimuli : process
    begin
        for j in 0 to 10 loop
	    i <= std_logic_vector(to_unsigned(j, 18));
            wait for 1 ns;
        end loop;
    wait;
    end process;

    uut : entity work.bug port map(i => i, o_bug => o_bug);

end;

Here is the result of the simulation.

As you can see, it works in simulation.

Best regards,

Ivan

P.S. It has been almost two weeks that i am trying to prove you that such simple construct as A<=B does not work in this case. I have provided an VHDL example, the proof in the RTL view, now we are down to simulating the basic VHDL A<=B construct. This is really a very basic VHDL. You have multiple times sent me completely false and misleading information, which leads me to believe that you do not have experience with that language. Is there anybody in support with VHDL knowledge who might have a look at it? Because realizing that the problem here is not due to "coding issues"(what does it even mean anyway?) should not take more then 10 min.