Bug report: synthesis optimizes out the signal if data type is declared in generic package

Dear Ean,

you have not provided a solution to the bug, you have provided a workaround. By avoiding the use of generic package you have avoided the bug.

In the case I have presented, the Intel Quartus synthesis generates wrong design. It does not produce any error messages. And I also do not want to consider changing my architecture, because the code I wrote is valid VHDL and I expect Quartus to produce correct results from it. It also simulates fine in Modelsim.

I also do not need a workaround.

I just wanted to report a bug in the synthesis tool and to get it fixed.

Let's try again. Below I have provided an example, where the synthesis tool wrongly removes the whole connection. No errors are generated in Quartus.
I can also simulate this file in Modelsim and the connection is there.

Can you explain the behavior of the synthesis tool? Why is the whole connection to o_bug removed in this case?

library ieee;
use ieee.std_logic_1164.all;
use work.parallel_pixel_type_pkg.all;

entity bug is
    port(
        i     : in  std_logic_vector(17 downto 0);
        o_bug : out std_logic_vector(16 downto 0)
	  );
end entity;

architecture rtl of bug is
    signal sp      : test_type_t;
begin
 sp.pixel_data(0) <= i;
 o_bug <= sp.pixel_data(0)(16 downto 0);
end rtl;

If you need any more information, let me know.

Best regards,

Ivan