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Ivan00's avatar
Ivan00
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4 years ago

Bug report: synthesis optimizes out the signal if data type is declared in generic package

When the data type is declared in the generic package, the synthesis tool removes the signal completely when array slice is used on the right side of the assignment. I have condensed it to the follow...
YEan's avatar
YEan
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4 years ago

Hi Ivan,

If the bus length of input and output were different the Quartus will show error messages. You may consider to change the architecture in your design to fulfill your requirement.

Thanks,

Ean

Ivan00's avatar
Ivan00
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4 years ago

Hi Ean,

I want to connect 16 lower bits of the 17 bit signal to the external port, i.e.

signal a : std_logic_vector(16 downto 0);

signal b: std_logic_vector(15 downto 0);

b <= a(15 downto 0);

I have provided an example where it does not work. The example is not from my working project, I have stripped it down in order to easily demonstrate the issue.

Can you see the problem here?

b(15 downto 0) must be connected to a(15 downto 0), but it is removed.

Best regards,

Ivan

  • YEan's avatar
    YEan
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    4 years ago

    Hi Ivan,

    Yes, this option works fine when there are only one statement in the architecture. If there are two concurrent statements in the architecture as shown in the previous example, the most significant signal will be connected and the least significant signal will not be connected.

    You may refer to this https://stackoverflow.com/questions/12144019/how-to-write-to-two-output-ports-from-inside-architecture-in-vhdl on how to connect one input to multiple outputs.

    Thanks,

    Ean

    • Ivan00's avatar
      Ivan00
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      4 years ago

      Hi Ean,

      the link to the stack overflow page does not apply here, it is completely different issue.

      I have simplified my example further, so that two ports do not mislead anybody. Now there is only one signal at the output, and it is still not connected. I hope you can see the issue this time.

      library ieee;
use ieee.std_logic_1164.all;
use work.parallel_pixel_type_pkg.all;

entity bug is
    port(
        i     : in  std_logic_vector(17 downto 0);
        o_bug : out std_logic_vector(16 downto 0)
	  );
end entity;

architecture rtl of bug is
    signal sp      : test_type_t;
begin
 sp.pixel_data(0) <= i;
 o_bug <= sp.pixel_data(0)(16 downto 0);
end rtl;

      Best regards,

      Ivan

      • YEan's avatar
        YEan
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        4 years ago

        Hi Ivan,

        Noted. I have tried another way. Adding a 17 bits signal, sp2, to connect the input i and output o_bug.

        --

        architecture rtl of bug is
        signal sp : test_type_t;
        signal sp2 : std_logic_vector(16 downto 0);

        begin

        sp.pixel_data(0) <= i;
        sp2 <= i(16 downto 0);
        o_ok <= sp.pixel_data(0);
        o_bug <=sp2;

        end rtl;

        --

        Thanks,

        Ean