New Contributor
New ContributorHi Ean,
i have chosen different output bus size in order to demonstrate the bug. The bug manifests itself when subscript is used on the right side.
When I resize the bus, the o_bug[16 downto 0] must be connected to i[16 downto 0], only bit 17 should be removed. Instead the whole connection is removed.
This happens only if the type test_type_t is defined in a generic package.
Best regards,
Ivan
ContributorHi Ivan,
If the bus length of input and output were different the Quartus will show error messages. You may consider to change the architecture in your design to fulfill your requirement.
Thanks,
Ean
New ContributorHi Ean,
I want to connect 16 lower bits of the 17 bit signal to the external port, i.e.
signal a : std_logic_vector(16 downto 0);
signal b: std_logic_vector(15 downto 0);
b <= a(15 downto 0);
I have provided an example where it does not work. The example is not from my working project, I have stripped it down in order to easily demonstrate the issue.
Can you see the problem here?
b(15 downto 0) must be connected to a(15 downto 0), but it is removed.
Best regards,
Ivan
ContributorHi Ivan,
Yes, this option works fine when there are only one statement in the architecture. If there are two concurrent statements in the architecture as shown in the previous example, the most significant signal will be connected and the least significant signal will not be connected.
You may refer to this https://stackoverflow.com/questions/12144019/how-to-write-to-two-output-ports-from-inside-architecture-in-vhdl on how to connect one input to multiple outputs.
Thanks,
Ean
