Bug report: Quartus will not load correct library in VHDL

Hello, I am a software-engineer and try to design circuits as a hobby.

-- synthesis library my_lib
library ieee, arithmetic;
use ieee.std_logic_1164.all;
use arithmetic.std_logic_arith.all;
entity calc is
    port (
        x: in std_logic_vector(63 downto 0);
        y: in std_logic_vector(63 downto 0);
        z: out std_logic_vector(63 downto 0)
    );
end;
architecture calc of calc is
begin
    z <= x + y;
end;
-- synthesis library my_lib2
library ieee, arithmetic;
use ieee.std_logic_1164.all;
use arithmetic.std_logic_arith.all;
entity calc is
    port (
        x: in std_logic_vector(63 downto 0);
        y: in std_logic_vector(63 downto 0);
        z: out std_logic_vector(63 downto 0)
    );
end;
architecture calc of calc is
    signal b: std_logic_vector(127 downto 0);
begin
    b <= x * y;
    z <= b(63 downto 0);
end;

library ieee, arithmetic;
use ieee.std_logic_1164.all;
use arithmetic.std_logic_arith.all;
entity delay is
    generic (
        L : integer
    );
    port (
        clock : in std_logic;
        x : in std_logic_vector(L - 1 downto 0);
        y : out std_logic_vector(L - 1 downto 0)
    );
end;
architecture delay of delay is
    signal d : std_logic_vector(L - 1 downto 0);
begin
    process (clock)
    begin
        if clock 'event and clock = '1' then
            d <= x;
        end if;
    end process;
    y <= d;
end;
library ieee, arithmetic;
use ieee.std_logic_1164.all;
use arithmetic.std_logic_arith.all;
library my_lib;
use my_lib.all;
use work.all;
entity main is
    port (
        CLOCK_125_p : in std_logic;
        LEDG : out std_logic_vector(7 downto 0)
    );
end;
architecture main of main is
    constant L: integer := 64;
    signal c: std_logic_vector(L - 1 downto 0)
        := (
            0 => '1',
            1 => '1',
            others => '0'
        );
    signal d: std_logic_vector(L - 1 downto 0);
begin
    i0: calc
        port map(c, c, d);
    
    i1: delay
        generic map(L => L)
        port map(CLOCK_125_p, d, c);
    
    process (CLOCK_125_p) is
    begin
        if CLOCK_125_p 'event and CLOCK_125_p = '1' then
            LEDG(7 downto 0) <= d(L - 1 downto L - 8);
        end if;
    end process;
end;