Honored Contributor
Honored Contributor> VHDL does not support polymorphism (in a programming sense).
Sorry, word is bad. Select the body of the modules before the compile, not at the run-time, that I just want to say. > For now,... Hmm, I think numbering-solution still has a conflict-problem. Why do not you share the library? Or why do not you use many libraries that you had written? For example, if have sufficiently long bit vectors, the my module for simple addition is larger but faster than build-in one, but it defines many sub-modules and I afraid the naming conflicts. When the conflicts occurred, how to fix it? Project-level-switching-solution seems a good idea. I will consider the way. > And then... I do not like to use compile options instead of pragmas, but there are no way to recognize it. hmm... I am going to write a script for the libraries and the ModelSim, and reform libraries are mixed into a file. post script: I have sent the problem# 11262015 to the mySupport, but I do not have e-mail that is associated to the university/company, in she said "the security reason" (nevertheless I do not want to contact by e-mail), it seems rejected. Could you please raise if the bug is a problem, Mr. Tricky?
