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Altera_Forum's avatar
Altera_Forum
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13 years ago

[Bug report QII 12.0] Bug during analysis and elaboration - multiple drivers possibl

Hi, it is possible to synthesize VHDL Code where multiple constrant drivers drives the same signal from 2 different processes. In the first process i treat an failuresignal normaly. When i want to drive the same Signal in a secound process in a if-loop the analysis tell me thats not possible. BUT when i want to drive the Signal in the second process in a case-instrucion in the "when others" state, then the analysis does not alert and the project synthesizes what is actually not allowd! Greez Dustin

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    W/O having had any look into the code I would assume that your's case statement is (as it should) be complete in itself, i.e. all conditions are covered by their own "when xyz =>" statement. Thus the "when others =>" never get's active and is thus removed by the compiler, also removing the not allowed two driver for one signal condition... If this is a correct assumption, remove the "when others" and replace the last when condition by when others (thus the when others condition is a valid one). This modification should bring up the error message of two drivers for one signal :-)