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EGrub's avatar
EGrub
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

BUG in simulation library for dcfifo_mixed_widths with Modelsim

If a dcfifo_mixed_widths is used (because I need the mixed width) but write and read side getting the same clock signal then simulation fails. With the read request signal the output changes immedia...
EGrub's avatar
EGrub
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Hi Khai Chein!

No I can not share my testbench, because I did not build a testbench around the FIFO. I integrated the FIFO in my own module and tested that module. Additionally you would not be able to start it as it is a co simulation of system verilog and C++

I used # to delay signals.

Best regards,

Erich