Bug in Quartus II

Note that all asynchronous presets will get converted to asynchronous clears and a not-gate will be placed before and after the register. So when the register powers-up to 0 or is cleared to 0, the not-gate after it will invert it so it looks like a 1. All logic going into the register will get inverted going in and out. So from a system level, everything works fine, but if you look at that register by itself in a simulation(or with SignalTap), it will look like it's behaving the opposite of what it should. There should be a table in the synthesis report about Inverted Registers, although I wish they would change the register name in a way that would make it recognizable without going to that table. In FPGAs, these extra inversions are generally free. The major place they aren't is I/O registers since there is no LUT between the register and the I/O port, but the I/O registers actually have a real preset.