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DGall10's avatar
DGall10
Icon for New Contributor rankNew Contributor
6 years ago

Bug fix for Quartus 13 .0 or 13.0 sp1 that fixes OR gates acting like AND gates and AND gates acting like OR gates

HI, Im using a RioRand and discovered that when I OR 2 signals either in VHDL or schematic they act like an AND gate and ANDing 2 signals acts like an OR gate. IS there a fix for this?
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Daryl,

Active low /active high configuration is used to tell under what logical condition given circuit is ON/OFF.

Example say Active-LOW button means that when you press/close the switch, then the signal sent to the FPGA will be LOW/Logic 0.

Active-LOW LED means that when we give logic '0' from FPGA than signal send to LED is to ON.

Please go through google for more information on it.

Regards

Anand