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DGall10's avatar
DGall10
Icon for New Contributor rankNew Contributor
6 years ago

Bug fix for Quartus 13 .0 or 13.0 sp1 that fixes OR gates acting like AND gates and AND gates acting like OR gates

HI, Im using a RioRand and discovered that when I OR 2 signals either in VHDL or schematic they act like an AND gate and ANDing 2 signals acts like an OR gate. IS there a fix for this?
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Daryl,

  1. You can check RTL viewer to confirm gate implemented.
  2. Check the simulation.
  3. Check the board schematic for switch/led configuration(Active-LOW or Active-HIGH).

I think you are using board with Active-LOW configuration.

Regards

Anand

  • ak6dn's avatar
    ak6dn
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    You don't indicate what pins your switches connect to, but based on your comment about the pullups enabled I believe they are implemented as active low, so when you push the switch the input goes to '0', normally it will be a logic '1'.

    Your LED drivers on the schematic (LED1, LED2) are active low as well. So you need to drive the output to logic '0' to light the LED.