Back when I was an intern I learned VHDL using the tutorials built into Aldec's editor and thought they were pretty good. I think the editor was also a simulator but I haven't used it in 10+ years so I'm not sure those tutorials are still around. Once you learn one language learning the other isn't too bad, if you have a choice as to which you learn and if you have a software background you might have an easier time with Verilog since it resembles C a little bit. Verilog is a double edge sword, it's a bit more loose than VHDL which I find make it quicker to code, but it also lets you get away with things that will bite you if you are not careful. When you learn about either language make sure to pay extra attention to the distinction between synthesizable vs simulation coding, if you mix them up you will probably run into some confusing problems.
Last but not least whatever you use to learn either language, don't rely on it as your only source. I would google search and look at code fragments, and I'd print a reference card and have it handy while you are coding.