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Altera_Forum
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11 years ago

bitwrite memory model for altera FPGAs

hi, i know how to make generic byte write, word write memory models in verilog for FPGAs. but is there any way of making a bit write memory model for altera FPGAs? i have looked online q...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

i guess i've managed a work-around for now - used the alteraIP and generated a memory block and instantiated it 8 times. and in each instance, i write just 1 bit (using the wren signal of the block). it is an expensive way of doing things but at least it wont induce 2 - 3 cycle delay (or more) if i try and code the memory model myself. esp. because in my functional sim, i cant have more than 1 cycle delay in the reads/writes.

thanks.

z.