bitwrite memory model for altera FPGAs

i guess i've managed a work-around for now - used the alteraIP and generated a memory block and instantiated it 8 times. and in each instance, i write just 1 bit (using the wren signal of the block). it is an expensive way of doing things but at least it wont induce 2 - 3 cycle delay (or more) if i try and code the memory model myself. esp. because in my functional sim, i cant have more than 1 cycle delay in the reads/writes.