Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

bitwrite memory model for altera FPGAs

hi,

i know how to make generic byte write, word write memory models in verilog for FPGAs. but is there any way of making a bit write memory model for altera FPGAs?

i have looked online quite a lot but couldn't find one. and the memory model i am making ends up having a couple of cycles of delay in reads and write (because of the bit-write nature). so if someone has worked with bitwrite memory models or knows where to find generic code for them (online link), that would be great.

thanks in advacne for the help.

z.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    i know how to make generic byte write, word write memory models in verilog

    --- Quote End ---

    Post some examples of your code and I suspect we can help with code consistent with what you have already.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    i guess i've managed a work-around for now - used the alteraIP and generated a memory block and instantiated it 8 times. and in each instance, i write just 1 bit (using the wren signal of the block). it is an expensive way of doing things but at least it wont induce 2 - 3 cycle delay (or more) if i try and code the memory model myself. esp. because in my functional sim, i cant have more than 1 cycle delay in the reads/writes.

    thanks.

    z.