bit shift and extract

Thank you dear Moderator! Thank you Cris72!!! First, you're absolutely right, I'm absolutely rather fighting with VHDL than understanding what I'm doing. Thus I really appreciate your answers!! I appologize, but please be patient with guys like me :)

So, for my beginner's project I'm trying to play with the 7-seg display of my DE1-SoC (Terasic) board. I recycled two example codes I did so far:

One that counts and uses actually a package ("package is..") implementation for displaying a 4-digit decimal number. Another one I use as "behavioral" (the thing with "architecture is..", right?). I imported the display and package into QSYS and did a top level .vhd. In order to obtain input from Linux via an AVALON MM interface. For decimal, the setup worked fine. But now I want to print hex numbers on the 7-seg display instead of decimal. Actually I now see that by AVALON MM I already obtain an std_logic_vector which I convert into integer, so this is probably then not even necessary!?

Perhaps best is I post the specific "package" as working original, with some comments.. My idea actually is instead of separating thousands, houndreds, tens and ones, to separate into the 4-tuple of 32 bit values for my hex display. Later I'd like to print by switch setting the first, second or... 4-tuple of bigger hex numbers as well.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package my is
	-- function declaration: has one return value
	function int_to7seg(a:integer) return std_logic_vector;
	
	-- procedure declaration: has several return values
	procedure seg_ctrl(signal number: in integer; signal digit1, digit2, digit3, digit4: out integer range 0 to 9);
end my;
package body my is
	function int_to7seg(a:integer) return std_logic_vector is
	variable result: std_logic_vector(6 downto 0);
	begin
		case a is
		-- since segments are active when LOW(0), the function must return 1111001 for '1'
			when 0 => result := "1000000"; -- display 0
			when 1 => result := "1111001";
			when 2 => result := "0100100";
			when 3 => result := "0110000";
			when 4 => result := "0011001";
			when 5 => result := "0010010";
			when 6 => result := "0000010";
			when 7 => result := "1111000";
			when 8 => result := "0000000";
			when 9 => result := "0010000"; -- extend for values up to 15
			when others => result:=(others=>'0'); -- rest all to '0'
		end case;
		return result;
	end int_to7seg;
	-- split the number, if the number is bigger than e.g. 999,
	-- divide it by 1000, the result is the number of the 4th
	-- 7-seg-display
	procedure seg_ctrl(signal number: in integer; signal digit1, digit2, digit3, digit4: out integer range 0 to 9) is
	variable temp: integer range 0 to 9999; -- I changed this to a different limit
	variable d1: integer range 0 to 9;-- I changed this to a different limit
	variable d2: integer range 0 to 9;-- I changed this to a different limit
	variable d3: integer range 0 to 9;-- I changed this to a different limit
	variable d4: integer range 0 to 9;-- I changed this to a different limit
	begin
		temp:= number;
		-- thousands
		if(temp>999)then
-- TODO for this position (I renamed d3, starting from d0), I'd like to cut out the specific bits
			d4 := temp/1000;
			temp := temp-d4*1000;
		else
			d4 := 0;
		end if;
		-- houndreds
		if(temp>99)then
			d3 := temp/100;
			temp := temp-d3*100;
		else
			d3 := 0;
		end if;
		-- tens
		if(temp>9)then
			d2 := temp/10;
			temp := temp-d2*10;
		else
			d2 := 0;
		end if;
		-- ones
		d1 := temp;
		-- translate to digits
		digit1 <= d1;
		digit2 <= d2;
		digit3 <= d3;
		digit4 <= d4;
	end seg_ctrl;
end my;

what would be the "standard" way to perform this in vhdl?