bit shift and extract

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Hi everyone!

i want to shift a number 24 bit to the right (cut off), and extract the remaining 8 bit. how to do it in vhdl?

a = b >>24 & 0xff;

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I dont think you quite understand VHDL is not a programming language. As such, you can easily just pull out the bits you want:

signal a : std_logic_vector(31 downto 0);
--pull out some bits
output <= a(19 downto 12);

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So far I tried to work with srl, shift_right(), '&' and 'and' operators - actually nothing worked out. Running everything within a procedure, I have the following declarations

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Why are you in a procedure? is this behavioural code? or are you trying to synthesise? please post the whole code so we can see what you're actually trying to do

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(...)
variable temp: integer range 0 to 65535;
variable d3: integer range 0 to 15;
(...)
-- and currently apply it the following way
d3 := to_integer(shift_right(unsigned(temp), 24)) and "11111111";

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In VHDL, an integer is not type with individual bits - you need to convert it to a more appropriate type like signed or unsigned to access bits or concatenate bits. The code snippet you posted doesnt make any sense.

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first I left away any "and" construction: d3 := to_integer(shift_right(unsigned(temp), 24));

Errors I obtain:Error: VHDL Use Clause error at increment_display.vhd(61): more than one Use Clause imports a declaration of simple name "unsigned" -- none of the declarations are directly visible

...so I removed "unsigned()"

Error: VHDL error at increment_display.vhd(61): can't determine type of object at or near identifier "shift_right" -- found 0 possible types

...so I removed to_integer(), actually everything was already devined as integer, no?

Error: VHDL Qualified Expression error at increment_display.vhd(61): SHIFT_RIGHT type specified in Qualified Expression must match integer type that is implied for expression by context

...hum...

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This is because you have used both ieee.std_logic_arith and ieee.numeric_std in your file. You need to delete the non-standard std_logic_arith from the use clauses and these errors will go away.

Actually, I could not find much or any example snippets on shifting and extracting, is there a totally different way of doing this in VHDL?

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I'm not sure about the syntax, but this is the usual way to extract bits in HDL:

variable tvect : std_logic_vector(7 downto 0);

tvect := conv_std_logic_vector(temp);

d3 := conv_integer(treg(31 downto 24);

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THis is non-standard VHDL.