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Altera_Forum's avatar
Altera_Forum
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13 years ago

Best way to interface my CPU

Hello, I am wondering what is the best way to interface my 32-bit RISC CPU. I need to interface it with the sdram memory, the flash memory, and possibly the sram memory. I will also need to dedicate ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I had a quick look at the design you sent me and didn't find anything wrong. I saw also in your test software that you are using the IOWR macro and the base address constant defined in system.h. This is better as it will avoir cache and wrong address problems.

Here are a few suggestions to help debug further:[list][*]add a system id component to the QSys project, and configure the IDE to check it before uploading the software. That way if for whatever reason the FPGA image isn't in sync with the software BSP, you'll get an error message[*]add a JTAG UART component and put a printf() in your test software, to be sure your CPU is actually running and isn't stuck somewhere.[/list]As an example you could test with this function:
void main()
{
	int x=0;
	while(1)
	{
		IOWR(TEST_SLAVE_0_BASE,0,x++);
		printf("wrote something\n");
	}
}