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How does it look?
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Not too bad. Except that chip_select is redundant, since read and write perform that function.
You're missing two potentially useful signals; waitrequest and readvalid. While these signals are not mandatory, including them makes it easier to use your component outside of Qsys, i.e., you can create an Avalon system without using Altera's tools by directly connecting masters to slaves, in which case the slaves need to have the same controls as the master (since there is no Qsys fabric).
The two signal implementations are pretty simple.
1) waitrequest
waitrequest is used to acknowledge a transaction, in your case, you can always accept transactions, so your waitrequest output needs to be low after reset. The spec indicates that waitrequest must be high during reset, so you need a simple register:
-- ------------------------------------------------------------
-- Wait-request handshake
-- ------------------------------------------------------------
--
process(clk, rstN)
begin
if (rstN = '0') then
-- High during reset per Avalon verification suite
waitrequest <= '1';
elsif rising_edge(clk) then
waitrequest <= '0';
end if;
end process;
2) readdatavalid
readdatavalid needs to assert when the data is valid on the output of the component and readdatavalid cannot assert during the same clock phase as the read transaction is accepted (per the Avalon spec), so you need
-- ------------------------------------------------------------
-- Read data valid pipeline
-- ------------------------------------------------------------
--
process(clk, rstN)
begin
if (rstN = '0') then
readdatavalid <= '0';
elsif rising_edge(clk) then
readdatavalid <= read;
end if;
end process;
Cheers,
Dave
Honored Contributor
