Best way to interface my CPU

Ok I figured out how to get it to work with VHDL code. I figured out most of the Avalon specifying is done when you add something as a new component. Now I managed to make a slave Avalon-MM device. Well the VHDL code only. How does it look?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity test_slave is
port (
      clock : in std_logic;
		resetn : in std_logic;
		read : in std_logic;
		write : in std_logic;
		chip_select : in std_logic;
		
		byte_enable : in std_logic_vector(3 downto 0);
		writedata : in std_logic_vector(31 downto 0);
		readdata : out std_logic_vector(31 downto 0);
		to_lights : out std_logic_vector(31 downto 0)
		
     );
end test_slave;
architecture Behavioral of test_slave is
signal the_register : std_logic_vector(31 downto 0);
begin
process(clock,resetn)
begin
if resetn = '0' then
	the_register <= (others => '0');
elsif rising_edge(clock) then
	if chip_select = '1' then
		if write = '1' then
			if byte_enable(0) = '1' then
				the_register(7 downto 0) <= writedata(7 downto 0);
			end if;
			if byte_enable(1) = '1' then
				the_register(15 downto 8) <= writedata(15 downto 8);
			end if;
			if byte_enable(2) = '1' then
				the_register(23 downto 16) <= writedata(23 downto 16);
			end if;
			if byte_enable(3) = '1' then
				the_register(31 downto 24) <= writedata(31 downto 24);
			end if;
		end if;
	end if;
end if;
end if;
end process;
if chip_select = '1' then
	if read = '1' then
		readdata <= the_register;
	end if;
			
end if;
to_lights <= the_register;
end Behavioral;