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The Keep directive seems to have worked!!!
I did have hold time optimization setting to all paths but it does not seem to force the necessary routing conditions.
Thank you for your interest.
The interface is just a simple three wire serial interface running at around 25 - 50 MHz. So it is a source synchronous interface. The CLK signal is generated by dividing down the main clock by 2 using simple logic and the CS_L signal is driven out of the state machine. Since it is relatively low frequency it is ok if the CS_L delay varies a bit as long as it is sometime between 1.5 and 10 nsec after the CLK signal. I was going to put the delay in the CS_L path. We are using Stratix II and I run slow and fast models Certainly I agree with you there should be better ways to do this.
Pletz: It would be great to get a second opinion on my constraints if your interested.
# Create clock for IO timing
create_generated_clock -name VDAC_CLK_PIN -source [get_pins $CLKD_VDAC] -divide_by 2 [get_registers $CLKIO_VDAC]
set vdac_clocks [get_clocks $CLKD_VDAC]
foreach_in_collection clk $vdac_clocks {set vdac_period [get_clock_info $clk -period]}
set vdac_max_delay [expr ($vdac_period - 2.0)]
# CS timing
# setup time = 8 nsec, hold = 0 nsec (being conservative) skew 1 nsec.
set_output_delay -clock VDAC_CLK_PIN -reference_pin VDAC_SCLK_R
-add_delay -min -1.5 [get_ports {VDAC_SYNC_L}]
set_output_delay -clock VDAC_CLK_PIN -reference_pin VDAC_SCLK_R
-add_delay -max $vdac_max_delay [get_ports {VDAC_SYNC_L}]
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Hi jstander,
unfortunately I have not so much experience with TimeQuest, but I think your constraints are ok.
Maybe I have an (stupid)idea how to simplify your problem. Are data signals coming out of the "fast" clock domain ? Is latency an issue ?
Kind regards
Pletz
Honored Contributor
