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How critical is your output timing ? Using additional inverter makes your timing depending
on temperature, device speed, power supply and your routing. If you plan to use the FPGA for a product I think you will run into problems.
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Could you explain a little bit more how the output signals "CLK" and "CS_L" are generated?
It sounds for me that you try to implement a "source synchronous" interface. Is the output signal "CLK" directly derived from a input clock ? It would also help when you post the part of the SDC file , where you set your constraints.
Honored Contributor
