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How critical is your output timing ? Using additional inverter makes your timing depending
on temperature, device speed, power supply and your routing. If you plan to use the FPGA for a product I think you will run into problems.
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If the inserted delay is in a data path and if you analyze timing with all available process/voltage/temperature combinations (three combinations for 65 nm and one hot and one cold combination for older devices), then this should be OK (even though it's not a recommended design practice). I would be concerned about inserting delay in a clock path for any device family and especially for device families older than 65 nm.
The Fitter can insert routing delay in a data path to meet the minimum requirement if "Optimize hold timing" is set to "All paths" in "Fitter Settings". Also enable "Optimize fast-corner timing", especially if you get timing violations with the fast model without this enabled. If hold optimization in the Fitter works well enough for this design, it would be more convenient than inserting LCELLs.
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