--- Quote Start ---
Hi,
I am using TimeQuest, I have two signals CLK and CS_L both driven off the same clock that go to ports on the chip. I have them constrained to force CS_L to be delayed 1.5 nsec from CLK. TimeQuest is unable to do this so I get a timing violation.
I figured an easy way to add delay is to add a couple of back to back inverters so that the routing delay would add 500 to 1000 psec. But when I do this they get optimized away dispite setting Netlist Optimization to OFF for both nets. I also tried instantiating a not cell and turning Remove Redundant Logic Cells OFF but this didn't work either. In both cases it can not find the nets or cells in the assignment editor because they are optimized away already?
I don't want to go through the fuss of creating a clock and then skewing it with a PLL. I just wanted to insert an approximate delay.
Is there a better way to do this.
--- Quote End ---
How critical is your output timing ? Using additional inverter makes your timing depending
on temperature, device speed, power supply and your routing. If you plan to use the FPGA for a product I think you will run into problems.
Honored Contributor
