Ok, I'll see if I can find some VHDL tutorial.
Just one last help if possible for me to understand why I get this error(i've had this error before).
this following code shouldn't be working?
I get an error: "Error (10476): VHDL error at RCT.vhd(74): type of identifier "entrada" does not agree with its usage as "array_saida" type".
As far as I understand, entrada and saida is the same type of array.
---------PACKAGE---------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE matrizes IS
TYPE array_entrada IS ARRAY (0 TO 3, 0 TO 3) OF STD_LOGIC_VECTOR(3 downto 0);
TYPE array_saida IS ARRAY (0 TO 3, 0 TO 3) OF STD_LOGIC_VECTOR(3 downto 0);
END matrizes;
------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.matrizes.all;
ENTITY rct IS
PORT (
clk: IN STD_LOGIC;
entrada: IN array_entrada;
saida: OUT array_saida);
END rct;
ARCHITECTURE comportamento OF rct IS
BEGIN
saida<=entrada;
END comportamento;
Thank You!