Best way for a 3d matrix

Many things wrong with this style of code.

1. you have clock in your process sensitivity list but you dont use clock inside the process. This will NOT create registers when you synthesise it, even though it may appear in simulation to be a dual edge flip flop.

2. Usually an image would be stored in ram. With this code, you are just inputting an entire image. What happens when you get to an image that is 1280x720, or similar? all your resources disspear and you only have a limited number of input pins, plus there is no interface that I know of that could get this much data in parrallel into an FPGA.

3. You should never define your own arrays of std_logic, like I said before. There are already some defined arrays of std_logic - std_logic_vector, signed and unsigned. Use those to make life easy for you, dont create your own versions.

4. Personally, with each value as a pixel, I would probably use an integer type or unsigned type.

eg.

type image_t is array (0 to 3, 0 to 3) of integer range 0 to 255;

5. Why have you got 3 different array types that are all basically the same thing. If you had the entrada and saida as the same type, you wouldnt need the loop:

ENTITY rct IS
PORT (
   clk: IN STD_LOGIC;
   entrada: IN array_entrada;
  saida:  OUT array_entrada);
END rct;
.....
process(clk)
begin
  if rising_edge(clk) then
    saida <= entrada;
  end if;
end process;

6. And finally - stop trying to get ahead of yourself. I suggest you go back to the fundamentals of digital logic before you try and write any more VHDL. If you try and take this any further, you are going to get yourself into a state where if you want code that will actually work on an FPGA, you will have to start all over again.