Best approach for creating clock sources please?

Taking for example my last post, I have created an 8MHz clock enable based on my common 24MHz clock source.

When the enable is true, any process such as:

  proc_8MHz_freq : PROCESS (M24MHz)
  BEGIN
    IF RISING_EDGE(M24MHz) THEN
      IF en_uM8MHz='1' THEN
        --some_counter + 1
      END IF;
    END IF;
  END PROCESS proc_8MHz_freq;

Here, some_counter will +1, not a frequency of 8MHz, rather it will see a bust of M24MHz clocks for the 8MHz enable period. This is obvious and not what I want to have happen with some_counter.

Is there an elegant way to better create the en_uM8MHz enable signal such that only ONE clocking event drives some_counter?

Thanks again,

Andy