Forum Discussion
Altera_Forum
Honored Contributor
11 years agoYes, just the answer I was looking for! Spot on. :)
So, going back to my original post, could I rewrite it as below to suit what I need to achieve?
--The main clock source for everything is running at 24MHz
--Create an 8MHz & n8Mhz clock enable
proc_8MHz : PROCESS (nPowerSettleDelay, M24MHz)
BEGIN
IF nPowerSettleDelay='0' THEN
en_uM8MHz <= '1';
en_u_nM8MHz <= '0';
Next_State <= State_1;
ELSIF RISING_EDGE(M24MHz) THEN
CASE Next_State IS
WHEN State_1 =>
Next_State <= State_2;
en_uM8MHz <= '1'; -- 1
en_u_nM8MHz <= '0'; -- 0
WHEN State_2 =>
Next_State <= State_3;
en_uM8MHz <= '0'; -- 0
en_u_nM8MHz <= '1'; -- 1
WHEN State_3 =>
Next_State <= State_1;
en_uM8MHz <= '0'; -- 0
en_u_nM8MHz <= '0'; -- 0
END CASE;
END IF;
END PROCESS proc_8MHz;
--Do something that is @ 8MHz
proc_DoSomething_8MHz : PROCESS(M24MHz)
BEGIN
IF RISING_EDGE(M24MHz) THEN
IF en_uM8MHz THEN
--do something every @ 8MHz
END IF;
END IF;
END PROCESS proc_DoSomething_8MHz;
--Do something that is @ /8MHz
proc_DoSomething_n8MHz : PROCESS(M24MHz)
BEGIN
IF RISING_EDGE(M24MHz) THEN
IF en_u_nM8MHz THEN
--do something every @ /8MHz
END IF;
END IF;
END PROCESS proc_DoSomething_n8MHz;
Thanks Tricky, Andy