Best approach for creating clock sources please?

The following code:

signal cnt : unsigned(2 downto 0) := "000";
signal div_by_2, div_by_4, div_by_8 : std_logic;
process(clk)
begin
    if rising_edge(clk) then
        cnt     <= cnt + 1;
        
        div_by_2 <= cnt(0);
        
        if cnt(1 downto 0) = 0 then
            div_by_4    <= '1';
        else
            div_by_4    <= '0';
        end if;
        
        if cnt = 0 then
            div_by_8    <= '1';
        else
            div_by_8    <= '0';
        end if;
        
        
        if div_by_2 then
            --do something every 2 clocks
        end if;
        
        if div_by_4 then
            -- do something every 4 clocks
        end if;
        
        if div_by_8 then
            -- do something every 8 clocks
        end if;
    end if;
end if;

process(clk)
begin
    if rising_edge(clk) then
        cnt     <= cnt + 1;
    end if;
end process;
        
process(clk)
begin
    if rising_edge(clk) then
        div_by_2 <= cnt(0);
    end if;
end if;
        
        
process(clk)
begin
    if rising_edge(clk) then
        if cnt(1 downto 0) = 0 then
            div_by_4    <= '1';
        else
            div_by_4    <= '0';
        end if;
    end if;
end if;       
        
process(clk)
begin
    if rising_edge(clk) then
        if cnt = 0 then
            div_by_8    <= '1';
        else
            div_by_8    <= '0';
        end if;
    end if;
end if
        
process(clk)
begin
    if rising_edge(clk) then        
        if div_by_2 then
            --do something every 2 clocks
        end if;
    end if;
end if;
        
process(clk)
begin
    if rising_edge(clk) then        
        if div_by_4 then
            -- do something every 4 clocks
        end if;
    end if;
end if;
        
process(clk)
begin
    if rising_edge(clk) then
        if div_by_8 then
            -- do something every 8 clocks
        end if;
    end if;
end if;