Best approach for creating clock sources please?

Riiiiight.

So, reading into your kind response, in effect I can see that basically everything that is clock event driven should therefore be in ONE big process? I had often wondered what exactly was meant by 'clock enables' - not quite the same as an enable pin on an IC as I had thought of it.

Now I am wondering how to rewire 2,000 lines of my VHDL code to suit this approach (and if it is worth it TBH). LOL. Having said that, what I have written so far is 95% complete and seems to work, all be it with some issues that need sorting out. Like most 'code' the closer one gets to completion, the more difficult the bugs become.

Thank you again Mr. Tricky

Andy