Best approach for creating clock sources please?

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I know it is not 'good practice' to gate clocks to create another clock which is then used to clock say a latch or a register etc.

So, what is considered a good / acceptable clock source? The output of a state machine perhaps? The output of a counter?

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The only good clock is either a real clock or the output of a PLL, thats it. A state machine output and counter output are the same thing - a register, and these are bad. Using logic to create a clock is bad.

For what you are doing, you want clock enables. Ie. the enable is high for one clock in a number of clocks, and you clock all your logic using the same system clock. And then your logic looks like this:

process(clk)
begin
  if rising_edge(clk) then
    cnt <= cnt + 1;
  
    div_by_2 <= cnt (0);
    if cnt(1 downto 0) = "00" then
      div_by_4 <= '1';
    else
      div_by_4 <= '0';
    end if;
    if div_by_2 then
      --stuff happens at half the system clock
    end if;
    if div_by_4 then
      --stuff happens at 1/4 of the system clock
    end if;
    --etc
  end if;
end process;