Oups! Sure, sry!!! I copy&paste'd the wrong version...
The version, now a bit more tested, but still with the same issue: readdata does not get assigned, is here:
module avalonmm_algo(
input clk,
input start,
input reset,
output reg leds,
input write,
input writedata,
output reg readdata,
output done
);
parameter WAITING = 2'b00;
parameter WORKING = 2'b01;
parameter DONE = 2'b10;
reg stage; // init?
initial stage = WAITING;
assign done = (stage == DONE);
reg step;
initial step = 2'b00;
reg algo_in;
initial algo_in = 8'b0;
reg algo_out;
initial algo_out = 8'b0;
// STEP rules, DATA initialization and handling
always @(*)begin
if(stage == WAITING)begin
leds <= 4'b0001;
end if(stage == WORKING)begin
leds <= 4'b0010;
end if(stage == DONE)begin
leds <= 4'b0100;
// TODO: why is this always executed?
end else begin
leds <= 4'b1111;
end
end
// procedural assignments for registers
// clocked STAGE and STEP transition, here
always @(posedge clk)begin
if(reset)begin
stage <= WAITING;
step <= 2'b00;
algo_in <= 8'b0;
algo_out <= 8'b0;
end else if(start)begin
stage <= WORKING;
step <= 2'b00;
end else if(stage == WORKING)begin
case(step)
2'b00: begin
if(write)begin
algo_in <= writedata;
step <= 2'b01;
end
end
2'b01: begin
algo_out <= algo_in + 1'b1;
if(0 < algo_out)begin
step <= 2'b10;
end
end
2'b10: begin
readdata <= algo_out; // TODO why does this not assign?
if(0 < readdata)begin
step <= 2'b11;
end
end
2'b11: begin
stage <= DONE;
end
endcase
end
end
endmodule
Questions: as above and the comments I had, perhaps you still could have another look on it, and give me some hints?
Honored Contributor
