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Altera_Forum
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12 years ago

Basics - 2 inputs, 1 output + positive edges

Quartus II, version 10.1, Cyclone II. I'm newbie in Verilog. I need a block: module (input x1,x2, output reg Y); if (positive edge of x1) Y=0; if (positive edge of x2) Y=1; I trie...
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Altera_Forum
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12 years ago

You cannot have a signal being changed by two different processes. This would be the equivalent of having two registers with different clocks having their outputs tied together.

Generally you would use a clock signal for doing edge triggering. The signals you then wish to trigger off would be used as enables. IE.