Basic Verilog questions: sequential execution within a procedural block

First of all, combinatorial processes should always use simple procedural assignments '=', never non-blocking assignments (NBA) '<='. NBAs in Code 2 will cause that process to execute multiple times unnecessarily because the values of out1 and out2 are not visible the first time through.

You normally do not see any delays in RTL code unless that RTL code needs to interface with gate-level code in the same simulation. Those delays are only needed on the boundaries of the RTL code and usually specified with continuous assignments or buffers with delays added.

If your RTL code is made of simple Boolean equations, then the structure does not matter. But as soon as you start adding more procedural statements like if/else and case, etc., then you want to group things together in a single block so you don't have to repeat those statements.