Basic question about Signals

Hi,

Yes in hardware it is either logic 0/1.

But in simulation you can see uninitialized,unknown,Don't care etc

example:

signal I : integer range 0 to 3;
-- I will initialise to 0
signal X : std_logic;
-- X will initialise to 'U

Also unused signal in design can be seen in simulation but not implemented in hardware.

Go through Synthesizable and Nonsynthesizable vhdl design.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)