Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Basic Problems with altlvds_rx ipcore on CycloneV

Dear everyone, I have to receive LVDS data stream based on altlvds_rx on cycloneV device. LVDS data pairs are 500Mbps with accompany 250MHz clock(DDR mode). I set following parameters in the ipcore: ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

at the end what matters is who should look after such strage violations; the tool or the user.

You enter PLL rx clk as 300MHz(3.333 period as displayed by wizard) then you supply that clk and enter sdc as 3.333

If the tool gets it wrong then it is a bug by definition. I haven't seen anywhere in TQ advice about rounding issues with respect to figures for clk period. I also entered sdc as "300MHz" instead of period and ended up with same strange violations.

Certainly the device seems to achieve such speeds at periods below or above 3.333