Basic Problems with altlvds_rx ipcore on CycloneV

This is not how the PLL works, but how it is analyzed. Finite numbers are used to say where the edges occur, and so rounding does occur. When default setup and hold relationships are determined, it needs to be determined if it's a rounding issue or a real shift. That's the problem that had to be fixed. For jitter, that's part of clock uncertainty and calculated after the default setup and hold relationships are calculated and doesn't have an affect.