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Altera_Forum
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11 years ago

Basic Problems with altlvds_rx ipcore on CycloneV

Dear everyone, I have to receive LVDS data stream based on altlvds_rx on cycloneV device. LVDS data pairs are 500Mbps with accompany 250MHz clock(DDR mode). I set following parameters in the ipcore: ...
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Altera_Forum
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11 years ago

also notice that rx clk is not data clk but just ref for PLL which will read data on a gnerated clk to match 600Mbps and will then output a parallel clk at 1/10 of that.

The internal data clock will have some jitter.