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Altera_Forum
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11 years ago

Basic Problems with altlvds_rx ipcore on CycloneV

Dear everyone, I have to receive LVDS data stream based on altlvds_rx on cycloneV device. LVDS data pairs are 500Mbps with accompany 250MHz clock(DDR mode). I set following parameters in the ipcore: ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I don't see how rounding applies to PLL.

PLL does not store any digital values for clock rates (though it sets dividers digitally). It is based on phase locking back and forth.

If TQ passes 3.332 period and not 3.333 (slower even) then I assume a bug in the tool