Basic Problems with altlvds_rx ipcore on CycloneV

I haven't looked at the exact issue, but am pretty sure it's a rounding issue.

If you have a 3.333ns clock creating a 2x clock to capture the data(LVDS captures in SDR, not DDR, to avoid rise/fall variation), it's a 1.6665ns clock. Let's say that gets rounded to 1.666ns(I'm making this up, as I haven't looked at the exact details, it probably gets rounded up). Now let's say it's transfering data to a 3.333ns clock. The source clock has edges at 0, 1.666, 3.332ns, etc. The latch clock has edges at 0, 3.333ns. So our default setup relationship is 1ps. This is not what we want, as the default setup relationship should be 1.6665(or1.6666ns).

If you change your source to 3.3332ns, this goes away. I'm quite certain something like this is happening.