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Altera_Forum
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11 years ago

Basic Problems with altlvds_rx ipcore on CycloneV

Dear everyone, I have to receive LVDS data stream based on altlvds_rx on cycloneV device. LVDS data pairs are 500Mbps with accompany 250MHz clock(DDR mode). I set following parameters in the ipcore: ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

You have derive_pll_clocks, which constrains the PLL and puts multicycles on the transfers, so you should be fine then.