Basic Problems with altlvds_rx ipcore on CycloneV

You're getting a rounding issue that pushes the default off a whole cycle of the slow clock, and the whole thing fails. I got rid of the -waveform(I don't think this is the problem, it's just unnecessary when 50/50) and decreased your period by 1ps:

create_clock -name lvdsrx_inclk -period 3.332 [get_ports "rx_inclock"]

Note that there were some enhancements made to TQ to better understand clock relationship when they should have an integral relationship, but due to rounding they end up being off by an edge. The problem is this update was done after 28nm devices were out, and some users had already fixed their incorrect relationship through multicycles(we could have done that for your case too, I believe). So if we suddenly released the fix for 28nm, it would actually break the designs that had worked around it. Because of that it was rolled into newer families(Arria 10, etc.) only. I'm not sure if there's a way to enable it either, at least through the GUI.

(I'm out all week and just sneaking this in, so won't be able to reply...)