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Altera_Forum
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11 years ago

Basic Problems with altlvds_rx ipcore on CycloneV

Dear everyone, I have to receive LVDS data stream based on altlvds_rx on cycloneV device. LVDS data pairs are 500Mbps with accompany 250MHz clock(DDR mode). I set following parameters in the ipcore: ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Dear Rysc,

I have tidy-up my project and upload it in the attachment. It is a Quartus 14.0 project with lvds_rx ipcore as the top-module, and a sdc file constraining its input clock. Can you please compile the project and see the result? My final project integrates other modules and the result is the same. Thank you very much!