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Altera_Forum
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11 years ago

Basic Problems with altlvds_rx ipcore on CycloneV

Dear everyone, I have to receive LVDS data stream based on altlvds_rx on cycloneV device. LVDS data pairs are 500Mbps with accompany 250MHz clock(DDR mode). I set following parameters in the ipcore: ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Something is wrong with the requirements. You have a multicycle -start -setup of 10 and a multicycle -hold -end of 9. I would have thought your hold requirement would be 0ns, not 31.6667ns. The weird thing is your hold requirement with no exceptions(that means no multicycles) is 31.667ns. It is almost always 0, and should be here. Something strange is going on but I'm not quite sure what. I assume you're calling derive_pll_clocks in your .sdc(which is where the multicycles come from).

So the MCs seem right, just your initial relationships. I can't tell why though from the info given.